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cyusb330x/cyusb331x cyusb332x/cyusb230x hx3 usb 3.0 hub cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? +1-408-943-2600 document number: 001-73643 rev. *r revised january 25, 2018 hx3 usb 3.0 hub general description hx3 is a family of usb 3.0 hub controllers compliant with the u sb 3.0 specification revision 1.0. hx3 supports superspeed (ss), hi-speed (hs), full-speed (fs), and low-speed (ls) on all the p orts. it has integrat ed termination, pull-up, and pull-down res istors, and supports configur ation options through pin-straps to reduce the overall bom of the system. hx3 includes the following cy press-proprietary features: shared link?: enables extra downstream (ds) po rts for on-board connections i n embedded applications ghost charge?: enables charging of d evices connected to t he ds ports when no host is connected on th e upstream (us) port hx3 usb 3.0 hub features usb-if certified hub, tid# 330000060, 30000074 supports up to four usb 3.0-compliant ds ports ? all ports support ss (5 gbps), and are backward-compatible with hs (480 mbps), fs (12 mbps), and ls (1.5 mbps) ? ss and usb 2.0 link power management (lpm) ? dedicated hi-speed transact ion translators (multi-tt) ? led status indicators C sus pend, ss, and usb 2.0 operation shared link? for embedded applications ? each ds port can simultaneously connect to an embedded ss device and a remov able usb 2.0 device ? enables up to eight device connections enhanced battery charging ? each ds port complies with t he usb battery charging v1.2 (bc v1.2) specification ? ghost charge?: each ds port can emulate a dedicated charging port (dcp) when the host is not connected to the us port ? accessory charger adapter dock (aca-dock): enables charging and simultaneous data transfer for a smart phone or a tablet acting as a host compliant to bc v1.2 ? apple charging supported on all ds ports integrated arm ? cortex?-m0 cpu ? 16 kb ram, 32 kb rom ? configure gpios for overcurrent protection, power enable, and leds ? upgrade firmware using (a) i 2 c eeprom or (b) an external i 2 c master vendor-command support to implement a usb-to-i 2 c bridge ? firmware upgrade of an external assp connected to hx3 through usb ? in-system programming (isp) of the eeprom connected to hx3 through usb extensive configuration support ? pin-strap configuration fo r the following functions: ? vendor id (vid) ? charging support for each ds port ? number of active ports ? number of non-removable devices ? ganged or individual power switch enables for ds ports ? power switch polarity selection ? custom configuration modes supported with efuse, i 2 c eeprom, or i 2 c slave ? ss and usb 2.0 phy parameters ? product id (pid)/vid, manufacturer, and product string descriptors ? swap dp/dm signals for flexible pcb routing software features ? microsoft whql-certified for windows xp/vista/7/8/8.1 ? compatible with mac os 10.9 and linux kernel version 3.11 ? customize configuration para meters with the easy-to-use cypresss blaster plus software tool flexible packaging options ? 68-pin qfn (8 8 1.0 mm) ? 88-pin qfn (10 10 1.0 mm) ? 100-ball bga (6 6 1.0 mm) ? industrial temperature ra nge (C40 c to +85 c)
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 2 of 43 block diagram usb 2.0 phy ss phy port control usb?2.0? phy ss phy vbus detect four transaction translators routing logic usb 2.0 ss repeater us port control routing buffer and routing logic hub controller phy interface ds buffers us buffers hub controller 3.3 v pll arm cortex-m0 ram rom 26 mhz 1.2 v usb 2.0 phy ss phy port control usb 2.0 phy ss phy port control usb 2.0 phy ss phy port control i2c i2c_data i2c_clk usb 2.0 controller ss controller us port dm ssrxp/m dp sstxp/m vbus led ovr pwr ds port 1 dm ssrxp/m dp sstxp/m led ovr pwr ds port 2 dm ssrxp/m dp sstxp/m led ovr pwr ds port 3 dm ssrxp/m dp sstxp/m led ovr pwr ds port 4 dm ssrxp/m dp sstxp/m
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 3 of 43 contents architecture overview ......................................... ............ 4 ss hub controller ............................................. .......... 4 usb 2.0 hub controller ........................................ ....... 4 cpu ........................................................... .................. 4 i2c interface ................................................. ............... 4 port controller ............................................... .............. 4 applications .................................................. .................... 4 hx3 product options ........................................... ............ 5 product features .............................................. ................ 6 shared link ................................................... .............. 6 ghost charge .................................................. ............ 6 vendor-command support ....... ........... ........... ........... .7 aca-dock support .............................................. ........ 7 pin information ............................................... .................. 8 system interfaces .. ........... ........... ........... .......... .............. 24 upstream port (us) ............................................ ....... 24 downstream ports (ds1, 2, 3, 4) .............................. 2 4 communication interfaces (i2 c) ................................ 24 oscillator ....... ........... ........... ............ ........... ............... 24 gpios ......................................................... ............... 24 power control ................................................. ........... 24 reset ......................................................... ................ 24 configuration mode select .. .............. ............ ......... ... 24 configuration options ......................................... ....... 24 emi ........................................................... ........................ 31 esd ........................................................... ....................... 31 absolute maximum ratings ...................................... .... 32 electrical specifications ..................................... ........... 32 dc electrical characteristi cs ................................. .... 32 power consumption ............................................. ..... 33 ordering information .......................................... ............ 34 ordering code definitions ..................................... .... 35 packaging ..................................................... ................... 36 package diagrams .............................................. ............ 37 acronyms ...................................................... .................. 39 reference documents ........................................... ......... 39 document conventions .......................................... ....... 39 units of measure .............................................. ......... 39 silicon revision history ...................................... .......... 40 method of identification ...................................... ....... 40 document history page ......................................... ........ 41 sales, solutions, and legal information ...................... 4 3 worldwide sales and design s upport ......... .............. 43 products ...................................................... .............. 43 psoc? solutions ............................................... ....... 43 cypress developer community . ................................ 43 technical support ........... .................................. ........ 43
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 4 of 43 architecture overview the block diagram on page 2 shows the hx3 architecture. hx3 consists of two independent hub controllers (ss and usb 2.0), the cortex-m0 cpu subsystem, an i 2 c interface, and port controller blocks. ss hub controller this block supports the ss hub functionality based on the usb 3.0 specification. the ss hub controller supports the following: ss link power management (u0, u1, u2, u3 states) full-duplex data transmission usb 2.0 hub controller this block supports the ls, fs, and hs hub functionalities. it includes the repeater, frame timer, and four transaction trans- lators. the usb 2.0 hub controller b lock supports the following: usb 2.0 link power managemen t (l0, l1, l2, l3 states) suspend, resume, and rem ote wake-up signaling multi-tt (one tt for each ds port) cpu the arm cortex-m0 cpu subsyst em is used for the following functions: system configuration and initialization battery charging control vendor-specific command s for the usb-to-i 2 c bridge string-descriptor support suspend status indicator shared link support in embedded systems i 2 c interface the i 2 c interface in hx3 supports the following: i 2 c slave, master, and mult i-master configurations ? configure hx3 by an external i 2 c master in i 2 c slave mode ? configure hx3 from an i 2 c eeprom ? multi-master mode to share eeprom with other i 2 c masters in-system progra mming of the i 2 c eeprom from hx3s us port port controller the port controller block controls ds port power to comply with the bc v1.2 and usb 3.0 specificat ions. this block also controls the us port power in the aca-dock mode. control signals for external power switches are implemented within the chip. hx3 controls the external power switches at power-on to reduce in-rush current. the port controller block supports the following: overcurrent detection ss and usb 2.0 port indicators for each ds port ganged and individual power control modes automatic port numbering based on active ports applications standalone hubs pc and tablet motherboards docking station hand-held cradles monitors digital tvs set-top boxes printers
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 5 of 43 hx3 product options notes 1. ds1 and ds2 are shared link ports. 2. bga industrial grade packages are limited to 1 w of active po wer. for power calculations refer to table 10 on page 33 . table 1. hx3 product options features cyusb3302 cyusb3304 cyusb3312 cyusb3314 cyusb3324 cyusb3326 cyusb3328 cyusb2302 cyusb2304 number of ds ports 2 (usb 3.0) 4 (usb 3.0) 2 (usb 3.0) 4 (usb 3.0) 4 (usb 3.0) 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 8 (4 ss, 4 usb 2.0) 2 (usb 2.0) 4 (usb 2.0) number of shared link ports 000002 [1] 400 bc v1.2 yes yes yes yes yes yes yes yes yes aca-dock no no no no yes no yes no no external power switch control ganged ganged individual and ganged individual and ganged individual and ganged individual individual ganged ganged pin-strap support no no yes yes yes yes yes no n o i 2 c yes yes yes yes yes yes yes yes yes vendor command yes yes yes yes yes yes yes yes yes port indicators no no yes yes yes no no no no packages [2] 68-qfn, 100-ball bga 68-qfn, 100-ball bga 88-qfn, 100-ball bga 88-qfn, 100-ball bga 88-qfn, 100-ball bga 88-qfn, 100-ball bga 88-qfn, 100-ball bga 68-qfn, 100-ball bga 68-qfn, 100-ball bga temperature range industrial and commercial industrial and commercial industrial and commercial industrial and commercial industrial and commercial industrial and commercial industrial (88-qfn only) and commercial industrial and commercial industrial and commercial
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 6 of 43 product features shared link figure 1. application of shared link in a notebook shared link is a cypress-propr ietary feature that enables a usb 3.0 port to be split into an embedded ss port and a standard usb 2.0 port. shared link enables a maximum of eight ds ports from a four-port usb 3.0 hub. for example, if one of the ds ports is connected to an embedded ss device, such as a usb 3.0 camera, hx3 enables the system designer to reuse the usb 2.0 s ignals of that specific port to connect to a standard usb 2.0 port. figure 1 shows how shared link can be used i n an application. figure 2. ds port vbus control in shared link the shared link mode requires a separate vbus control for the removable usb 2.0 device and the embedded ss device. figure 2 shows the vbus cont rol implementation. to ensure that the embedded ss device does not fall back to usb 2.0 operation, an external power switch is required. this switch is controlled by hx3, which generates an output signal called dsx_vbusen_sl. this signal controls the vbus for the embedded device. dsx_pwren is another output signal generated by hx3 and controls vbus for the removable usb 2.0 device. for example, when an overcurrent condition occurs, dsx_pwren turns off the port power. ghost charge ghost charge is a cypress-proprietary feature for charging usb devices on the ds port when the us port is not connected to a host. for example, in a docking station with hx3 as shown in figure 3 , when the laptop is undocked, hx3 will emulate a dedicated charging port (dcp) to provide charge to a phone connected on a ds port. figure 3. ghost charge usb 3.0 example: shared link provide s six usb ports in a notebook d+ d- standard usb 2.0 port internal ss port sstx+ sstx- ssrx+ ssrx- usb 3.0 port split into ss port and standard usb 2.0 port usb 3.0 usb 2.0 wifi module ds4 pc chipset usb 3.0 host usb 2.0 ss (internal) usb 2.0 ss (internal) ds1 ds2 ds3 usb 3.0 camera us notebook pc motherboard hx3 hx3 4 2 6 usb 3.0 card reader 6 6 2 6 4 usb 3.0 port 6 usb 3.0 usb 3.0 superspeed phy usb 2.0 phy usb 3.0 ds port embedded superspeed device removable usb 2.0 device hx3 ssrxp/m sstxp/m dp dm vbus vbus dsx_vbusen_sl dsx_pwren charge a smartphone without do cking the notebook hx3 power to smartphone (hx3s downstream port) usb cable notebook pc undocked
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 7 of 43 when the us port is di sconnected from the host, hx3 detects if any of the ds ports are connected to a device requesting charging. it determines the charging method and then switches to the appropriate signaling based on the detected charging specification as shown in figure 4 . the hub either emulates a usb-compliant dedicated charging port by connecting dp and dm (see the bc v1.2 specification) or other supported proprietary charging schemes. figure 4. ghost charge implementation in hx3 ghost charge is enabled by default and can be disabled through configuration. refer to configuration options on page 24 . vendor-command support hx3 supports vendor-specific r equests and can also enumerate as a vendor-specific device. the vendor-specific request can be used to (a) bridge usb and i 2 c and (b) configure hx3. this feature can be used for the following applications: firmware upgrade of an exte rnal assp connected to hx3 through usb in-system programming (isp) of an eeprom c onnected to hx3 through usb aca-dock support in traditional usb topologies, the host provides vbus to enable and charge the connected devices. for otg hosts, however, an aca-dock provides vbus and a method to charge the host. hx3 supports the aca-dock standard (see bc v1.2 specifi- cation) by integrating the func tions of the adapter controller. figure 5 shows the aca-dock system. if the aca-dock feature is enabled, hx3 turns on the external power switch to drive vbus on the us port. to inform the otg host that it is connecte d to an aca-dock, the id pin is tied to ground using a resistor rid_a, 3 as shown in figure 5 . the aca-dock feature can be disabled using the configuration options on page 24 . for example, a bc v1.2 compliant phone such as a sony xperia (neo v) can be docked to a hx3-based aca-dock system. the phone acts as an otg host and the aca-dock charges the phone connected to the us port while also powering the four ds ports. figure 5. aca-dock support wall charger detector other charging scheme bc v1.2 scheme charging scheme detector battery charger power switch dm 5 v dsx_pwren dsx_ovrcurr usb battery-powered device hx3 ds port dp vbus hx3 power switch 5 v us_pwren vbus id to us otg enabled device pcb micro a plug vbus power source rid_a vbus note 3. 124 k ? is the recommended rid_a value as per bc v1.2 specification, b ut some portable devices use custom rid_a values.
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 8 of 43 pin information figure 6. hx3 68-pin qfn 2-port pinout 1 gnd 68-pin qfn 68 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 67 19 20 66 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 30 56 55 31 54 32 33 53 52 34 2 vdd_efuse vbus_ds suspend reserved1 reserved2 mode_sel[0] mode_sel[1] nc rref_ss dvdd12 vdd_io pwr_en ovrcurr resetn i2c_clk i2c_data avdd12 nc dvdd12 ds2_txp ds2_txm dvdd12 ds2_rxm ds2_rxp avdd12 ds1_txp ds1_txm dvdd12 ds1_rxm ds1_rxp avdd12 avdd12 xtl_out xtl_in avdd33 us_dp us_dm ds1_dm ds1_dp avdd33 ds2_dp ds2_dm avdd33 dvdd12 rref_usb2 dvdd12 avdd33 us_txm us_txp dvdd12 us_rxm us_rxp avdd12 dvdd12 avdd12 vbus_us nc nc nc nc nc nc nc nc nc nc nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 9 of 43 figure 7. hx3 68-pin qfn 4-port pinout 1 gnd 68-pin qfn 68 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 67 19 20 66 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 30 56 55 31 54 32 33 53 52 34 2 vdd_efuse vbus_ds suspend reserved1 reserved2 mode_sel[0] mode_sel[1] nc rref_ss dvdd12 vdd_io pwr_en ovrcurr resetn i2c_clk i2c_data avdd12 ds3_rxp ds3_rxm dvdd12 ds3_txp ds3_txm ds2_txp ds2_txm dvdd12 ds2_rxm ds2_rxp avdd12 ds1_txp ds1_txm dvdd12 ds1_rxm ds1_rxp avdd12 avdd12 xtl_out xtl_in avdd33 us_dp us_dm ds1_dm ds1_dp avdd33 ds2_dp ds2_dm ds3_dm ds3_dp avdd33 ds4_dp ds4_dm dvdd12 rref_usb2 dvdd12 avdd33 us_txm us_txp dvdd12 us_rxm us_rxp avdd12 ds4_txp ds4_txm dvdd12 avdd12 ds4_rxm ds4_rxp vbus_us
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 10 of 43 figure 8. hx3 100-ball bg a pinout for cyusb3302 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 nc nc nc avdd33 ds2_dm ds2_dp avdd33 us_dm us_dp avdd12 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 nc nc nc vdd_io vss avdd33 nc nc nc dvdd12 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 us_txm nc nc nc nc vss ds1_dp ds1_dm avdd12 ds1_rxm d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 us_txp nc nc dvdd12 vss dvdd12 vss dvdd12 vss ds1_rxp e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 dvdd12 rref_us b2 nc nc xtl_in xtl_out vdd_io ds1_txm vss dvdd12 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 us_rxm vss avdd33 mode_se l[1] dvdd12 ovrcur r resetn ds1_txp avdd12 ds2_rxp g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 us_rxp vbus_ds suspend reserve d1 mode_se l[0] vdd_io pwr_en i2c_data vss ds2_rxm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 avdd12 vbus_us vdd_efu se reserve d2 rref_ss vss ds2_txm ds2_txp nc avdd12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 vss avdd12 vss gpio nc i2c_clk nc nc vss nc k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 nc nc dvdd12 nc nc nc nc nc dvdd12 nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 11 of 43 figure 9. hx3 100-ball bg a pinout for cyusb3304 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 nc ds4_dm ds4_dp avdd33 ds2_dm ds2_dp avdd33 us_dm us_dp avdd12 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 nc nc nc vdd_io vss avdd33 nc nc nc dvdd12 c1 c2 c3 c4 c5 c6 c7 c8 c9 10 us_txm nc nc ds3_dp ds3_dm vss ds1_dp ds1_dm avdd12 ds1_rxm d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 us_txp nc nc dvdd12 vss dvdd12 vss dvdd12 vss ds1_rxp e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 dvdd12 rref_us b2 nc nc xtl_in xtl_out vdd_io ds1_txm vss dvdd12 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 us_rxm vss avdd33 mode_se l[1] dvdd12 ovrcur r resetn ds1_txp avdd12 ds2_rxp g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 us_rxp vbus_ds suspend reserve d1 mode_se l[0] vdd_io pwr_en i2c_data vss ds2_rxm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 avdd12 vbus_us vdd_efu se reserve d2 rref_ss vss ds2_txm ds2_txp nc avdd12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 vss avdd12 vss gpio nc i2c_clk nc nc vss ds3_rxm k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 ds4_txp ds4_txm dvdd12 ds4_rxp ds4_rxm nc ds3_txp ds3_txm dvdd12 ds3_rxp
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 12 of 43 table 2. 68-pin qfn, 100-ball b ga pinout for cyusb3302 and cyu sb3304 pin name type 68-qfn pin# 100-bga ball # description cyusb3302 cyusb3304 us port us_rxp i 9 g1 superspeed receive plus us_rxm i 8 f1 superspeed receive minus us_txp o 6 d1 superspeed transmit plus us_txm o 5 c1 superspeed transmit minus us_dp i/o 57 a9 usb 2.0 data plus us_dm i/o 58 a8 usb 2.0 data minus ds1 port ds1_rxp i 51 d10 superspeed receive plus ds1_rxm i 50 c10 superspeed receive minus ds1_txp o 47 f8 superspeed transmit plus ds1_txm o 48 e8 superspeed transmit minus ds1_dp i/o 60 c7 usb 2.0 data plus ds1_dm i/o 59 c8 usb 2.0 data minus ds2 port ds2_rxp i 45 f10 superspeed receive plus ds2_rxm i 44 g10 superspeed receive minus ds2_txp o 41 h8 superspeed transmit plus ds2_txm o 42 h7 superspeed transmit minus ds2_dp i/o 62 a6 usb 2.0 data plus ds2_dm i/o 63 a5 usb 2.0 data minus ds3 port nc ds3_rxp i 35 k10 superspeed receive plus nc ds3_rxm i 36 j10 superspeed receive minus nc ds3_txp o 38 k7 superspeed transmit plus nc ds3_txm o 39 k8 superspeed transmit minus nc ds3_dp i/o 65 c4 usb 2.0 data plus nc ds3_dm i/o 64 c5 usb 2.0 data minus ds4 port nc ds4_rxp i 15 k4 superspeed receive plus nc ds4_rxm i 14 k5 superspeed receive minus nc ds4_txp o 11 k1 superspeed transmit plus nc ds4_txm o 12 k2 superspeed transmit minus nc ds4_dp i/o 67 a3 usb 2.0 data plus nc ds4_dm i/o 68 a2 usb 2.0 data minus ovrcurr i 30 f6 ganged overcurrent input pwr_en i/o 29 g7 ganged power enable output nc i/o 25 na nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 13 of 43 reserved1 i/o 21 g4 this pin must be pulled high using a 10 k ? to vdd_io. reserved2 i 22 h4 this pin must be pulled high using a 10 k ? to vdd_io. mode select, clock, and reset mode_sel[0] i 23 g5 device operation mode select bit 0; refer to ta b l e 5 on page 24 mode_sel[1] i 24 f4 device operation mode select bit 1; refer to ta b l e 5 on page 24 xtl_out a 54 e6 crystal out xtl_in a 55 e5 crystal in resetn i 31 f7 active low reset input i2c_clk i/o 32 j6 i 2 c clock i2c_data i/o 33 g8 i 2 c data suspend i/o 20 g3 hub suspend status ind icator. this pin is asserted if both the ss and usb 2.0 hubs are in t he suspend state and is de-asserted when either of the hubs comes out of the suspend state. power and ground vdd_efuse pwr 19 h3 1.2 v normal operation, 2.5 v for programming. customers should connect to 1.2 v. avdd12 pwr 10, 16, 34, 46, 52, 53 a10, c9, f9, h1, h10, j2 1.2 v analog supply gnd pwr 40 b5, c6, d5, d7, d9, e9, f2, g9, h6, j1, j3, j9 gnd pin dvdd12 pwr 1, 3, 7, 13, 27, 37, 43, 49, b10, d4, d6, d8, e1, e10, f5, k3, k9 1.2 v core supply vbus _us pwr 17 h2 this pin must be connected to vbus from us port vbus_ds pwr 18 g2 this pin is used to power the apple-charging circuit in hx3. for bc v1.2 compliance testi ng, connect pi n to gnd. for normal operation, connect pin to local 5 v supply. avdd33 pwr 4, 56, 61, 66 a4, a7, b6, f3 3.3 v analog supply vdd_io pwr 28 b4, e7, g6 3.3 v i/o supply usb precision resistors rref_usb2 a 2 e2 connect pin to a precis ion resistor (6.04 k ?? 1%) to generate a current reference for usb 2.0 phy. rref_ss a 26 h5 connect pin to a prec ision resistor (200 ? 1%) for ss phy termination impedance calibration. table 2. 68-pin qfn, 100-ball b ga pinout for cyusb3302 and cyu sb3304 (continued) pin name type 68-qfn pin# 100-bga ball # description cyusb3302 cyusb3304 note 4. these pins are do not use (dnu); they must be left floating.
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 14 of 43 table 3. 68-pin qfn, 100-ball b ga pinout for cyusb2302 and cyu sb2304 pin name type 68-qfn pin# 100-bga ball # description cyusb2302 cyusb2304 us port nc i 9 g1 superspeed receive plus nc i 8 f1 superspeed receive minus nc o 6 d1 superspeed transmit plus nc o 5 c1 superspeed transmit minus us_dp i/o 57 a9 usb 2.0 data plus us_dm i/o 58 a8 usb 2.0 data minus ds1 port nc i 51 d10 superspeed receive plus nc i 50 c10 superspeed receive minus nc o 47 f8 superspeed transmit plus nc o 48 e8 superspeed transmit minus ds1_dp i/o 60 c7 usb 2.0 data plus ds1_dm i/o 59 c8 usb 2.0 data minus ds2 port nc i 45 f10 superspeed receive plus nc i 44 g10 superspeed receive minus nc o 41 h8 superspeed transmit plus nc o 42 h7 superspeed transmit minus ds2_dp i/o 62 a6 usb 2.0 data plus ds2_dm i/o 63 a5 usb 2.0 data minus ds3 port nc nc i 35 k10 superspeed receive plus nc nc i 36 j10 superspeed receive minus nc nc o 38 k7 superspeed transmit plus nc nc o 39 k8 superspeed transmit minus nc ds3_dp i/o 65 c4 usb 2.0 data plus nc ds3_dm i/o 64 c5 usb 2.0 data minus ds4 port nc nc i 15 k4 superspeed receive plus nc nc i 14 k5 superspeed receive minus nc nc o 11 k1 superspeed transmit plus nc nc o 12 k2 superspeed transmit minus nc ds4_dp i/o 67 a3 usb 2.0 data plus nc ds4_dm i/o 68 a2 usb 2.0 data minus ovrcurr i 30 f6 ganged overcurrent input pwr_en i/o 29 g7 ganged power enable output nc i/o 25 na nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 15 of 43 reserved1 i/o 21 g4 this pin must be pulled high using a 10 k ? to vdd_io. reserved2 i 22 h4 this pin must be pulled high using a 10 k ? to vdd_io. mode select, clock, and reset mode_sel[0] i 23 g5 device operation mode select bit 0; refer to ta b l e 5 on page 24 mode_sel[1] i 24 f4 device operation mode select bit 1; refer to ta b l e 5 on page 24 xtl_out a 54 e6 crystal out xtl_in a 55 e5 crystal in resetn i 31 f7 active low reset input i2c_clk i/o 32 j6 i 2 c clock i2c_data i/o 33 g8 i 2 c data suspend i/o 20 g3 hub suspend status ind icator. this pin is asserted if both the ss and usb 2.0 hubs are in t he suspend state and is de-asserted when either of the hubs comes out of the suspend state. power and ground vdd_efuse pwr 19 h3 1.2 v normal operation, 2.5 v for programming. customers should connect to 1.2 v. avdd12 pwr 10, 16, 34, 46, 52, 53 a10, c9, f9, h1, h10, j2 1.2 v analog supply gnd pwr 40 b5, c6, d5, d7, d9, e9, f2, g9, h6, j1, j3, j9 gnd pin dvdd12 pwr 1, 3, 7, 13, 27, 37, 43, 49, b10, d4, d6, d8, e1, e10, f5, k3, k9 1.2 v core supply vbus _us pwr 17 h2 this pin must be connected to vbus from us port vbus_ds pwr 18 g2 this pin is used to power the apple-charging circuit in hx3. for bc v1.2 compliance testi ng, connect pi n to gnd. for normal operation, connect pin to local 5 v supply. avdd33 pwr 4, 56, 61, 66 a4, a7, b6, f3 3.3 v analog supply vdd_io pwr 28 b4, e7, g6 3.3 v i/o supply usb precision resistors rref_usb2 a 2 e2 connect pin to a precis ion resistor (6.04 k ?? 1%) to generate a current reference for usb 2.0 phy. rref_ss a 26 h5 connect pin to a prec ision resistor (200 ? 1%) for ss phy termination impedance calibration. table 3. 68-pin qfn, 100-ball b ga pinout for cyusb2302 and cyu sb2304 (continued) pin name type 68-qfn pin# 100-bga ball # description cyusb2302 cyusb2304
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 16 of 43 figure 10. hx3 88-pin qfn 2-port pinout 88-pin qfn 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 18 19 20 21 22 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 65 49 48 47 46 45 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 us_rxp us_rxm us_txp us_txm us_dp us_dm us_ovrcurr us_pwren ds1_rxp ds1_rxm ds1_txm ds1_txp ds1_dm ds1_dp ds2_dp ds2_dm ds2_rxp ds2_rxm ds2_txm ds2_txp nc ds1_ovrcurr ds1_pwren ds1_amber ds1_green ds1_led_ss ds2_amber ds2_green ds2_ovrcurr ds2_pwren ds2_led_ss ds3_pwren ds3_amber ds3_ovrcurr ds3_green ds3_led_ss ds4_ovrcurr ds4_pwren/pwr_en4 ds4_amber ds4_green ds4_led_ss i2c_clk i2c_data resetn vdd_io dvdd12 rref_ss avdd12 vdd_efuse vbus_ds suspend reserved1 mode_sel[0] mode_sel[1] dvdd12 avdd12 gnd dvdd12 dvdd12 avdd12 avdd12 vdd_io avdd33 avdd33 avdd33 dvdd12 vdd_io rref_usb2 dvdd12 avdd33 dvdd12 avdd12 dvdd12 avdd12 vbus_us xtl_in xtl_out nc nc nc nc nc nc nc nc nc nc nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 17 of 43 figure 11. hx3 88-pin qfn 4-port pinout 88-pin qfn 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 18 19 20 21 22 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 65 49 48 47 46 45 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 us_rxp us_rxm us_txp us_txm us_dp us_dm us_ovrcurr us_pwren ds1_rxp ds1_rxm ds1_txm ds1_txp ds1_dm ds1_dp ds2_dp ds2_dm ds3_dm ds3_dp ds4_dp ds4_dm ds2_rxp ds2_rxm ds2_txm ds2_txp ds3_txm ds3_txp ds3_rxm ds3_rxp ds4_txp ds4_txm ds4_rxm ds4_rxp ds1_ovrcurr ds1_pwren ds1_amber ds1_green ds1_led_ss ds2_amber ds2_green ds2_ovrcurr ds2_pwren ds2_led_ss ds3_pwren ds3_amber ds3_ovrcurr ds3_green ds3_led_ss ds4_ovrcurr ds4_pwren/pwr_en4 ds4_amber ds4_green ds4_led_ss i2c_clk i2c_data resetn vdd_io dvdd12 rref_ss avdd12 vdd_efuse vbus_ds suspend reserved1 mode_sel[0] mode_sel[1] dvdd12 avdd12 gnd dvdd12 dvdd12 avdd12 avdd12 vdd_io avdd33 avdd33 avdd33 dvdd12 vdd_io rref_usb2 dvdd12 avdd33 dvdd12 avdd12 dvdd12 avdd12 vbus_us xtl_in xtl_out
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 18 of 43 figure 12. hx3 100-ball bga pinout for cyusb3312 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ds3_pwr en nc nc avdd33 ds2_dm ds2_dp avdd33 us_dm us_dp avdd12 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 ds2_ovr curr ds2_pwr en ds3_ambe r vdd_io vss avdd33 ds3_ovr curr ds3_gree n ds3_led_ ss dvdd12 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 us_txm ds1_ambe r ds2_led_ ss nc nc vss ds1_dp ds1_dm avdd12 ds1_rxm d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 us_txp ds1_led_ ss ds1_gree n dvdd12 vss dvdd12 vss dvdd12 vss ds1_rxp e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 dvdd12 rref_usb 2 ds2_gree n ds2_ambe r xtl_in xtl_out vdd_io ds1_txm vss dvdd12 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 us_rxm vss avdd33 mode_se l[1] dvdd12 ds4_ovr curr resetn ds1_txp avdd12 ds2_rxp g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 us_rxp vbus_ds suspend reserve d1 mode_se l[0] vdd_io ds4_pwr en i2c_data vss ds2_rxm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 avdd12 vbus_us vdd_efus e ds4_led_ ss rref_ss vss ds2_txm ds2_txp ds4_gree n avdd12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 vss avdd12 vss ds4_ambe r us_pwre n i2c_clk ds1_pwr en ds1_ovr curr vss nc k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 nc nc dvdd12 nc nc us_ovrc urr nc nc dvdd12 nc
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 19 of 43 figure 13. hx3 100-ball bga pin out for cyusb3314, cyusb332x a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ds3_pwr en ds4_dm ds4_dp avdd33 ds2_dm ds2_dp avdd33 us_dm us_dp avdd12 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 ds2_ovr curr ds2_pwr en ds3_amb er vdd_io vss avdd33 ds3_ovr curr ds3_gre en ds3_led _ss dvdd12 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 us_txm ds1_amb er ds2_led _ss ds3_dp ds3_dm vss ds1_dp ds1_dm avdd12 ds1_rxm d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 us_txp ds1_led _ss ds1_gre en dvdd12 vss dvdd12 vss dvdd12 vss ds1_rxp e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 dvdd12 rref_us b2 ds2_gre en ds2_amb er xtl_in xtl_out vdd_io ds1_txm vss dvdd12 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 us_rxm vss avdd33 mode_se l[1] dvdd12 ds4_ovr curr resetn ds1_txp avdd12 ds2_rxp g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 us_rxp vbus_ds suspend reserve d1 mode_se l[0] vdd_io ds4_pwr en i2c_data vss ds2_rxm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 avdd12 vbus_us vdd_efu se ds4_led _ss rref_ss vss ds2_txm ds2_txp ds4_gre en avdd12 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 vss avdd12 vss ds4_amb er us_pwr en i2c_clk ds1_pwr en ds1_ovr curr vss ds3_rxm k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 ds4_txp ds4_txm dvdd12 ds4_rxp ds4_rxm us_ovrc urr ds3_txp ds3_txm dvdd12 ds3_rxp
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 20 of 43 table 4. 88-pin qfn, 100-ball b ga pinout for cyusb331x and cyu sb332x pin name type pin# ball# description cyusb3312 cyusb3314 cyusb3324 cyusb3326 cyusb3328 us port us_rxp i 14 g1 superspeed receive plus us_rxm i 13 f1 superspeed receive minus us_txp o 11 d1 superspeed transmit plus us_txm o 10 c1 superspeed transmit minus us_dp i/o 71 a9 usb 2.0 data plus us_dm i/o 72 a8 usb 2.0 data minus us_ovrcurr i 39 k6 cyusb3324/3328: overcurrent dete ct input for us port in aca-doc k mode. if aca-dock mode is disabled using configuration options on page 24 , this pin must be pul led high u sing a 10 k ? to vdd_io. other part numbers: thi s pin must be pulled high using a 10 k ? to vdd_io. us_pwren [5] i/o 31 j5 cyusb3324/3328: vbus power enable output for us port in aca-doc k mode. if aca-dock mode is disabled using configuration options on page 24 , this pin can be left floating if pin-strap is not enabled. other part numbers: this pin can be left floating if pin-strap (pin# 63) is not enabled. pwr_sw_pol [6] this pin is called pwr_sw_pol in pin-strap config uration mode. ds1 port ds1_rxp i 61 d10 superspeed receive plus ds1_rxm i 60 c10 superspeed receive minus ds1_txp o 57 f8 superspeed transmit plus ds1_txm o 58 e8 superspeed transmit minus ds1_dp i/o 74 c7 usb 2.0 data plus ds1_dm i/o 73 c8 usb 2.0 data minus ds1_ovrcurr i 42 j8 overcurrent detect input for ds1 port ds1_pwren [5] i/o 38 j7 vbus power enable output for ds1 port. when the port is disable d, this pin is in tristate. ds1_cdp_en [6] this pin is called ds1_cdp_en in pin-strap config uration mode. ds1_amber [5] i/o 2 c2 led_amber output for ds1 port aca_dock [6] this pin is called aca-dock in pin-strap configuration mode. ds1_green [5] i/o 3 d3 cyusb3312/3314/3324: led_green output for ds1 port ds1_vbusen_sl [5] cyusb3326/3328: vbus power en able output for ss port 1 port_disable[0] [6] this pin is called port _disable[0] in pin-st rap configuration m ode. ds1_led_ss [5] i/o 4 d2 led_ss output for ds1 port port_disable[1] [6] this pin is called port _disable[1] in pin-st rap configuration m ode. notes 5. this pin can be configured as a gpio using custom firmware. f or information contact www.cypress.com/support . 6. for pin-strap configuration details, refer to ta b l e 6 on page 25 .
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 21 of 43 ds2 port ds2_rxp i 55 f10 superspeed receive plus ds2_rxm i 54 g10 superspeed receive minus ds2_txp o 51 h8 superspeed transmit plus ds2_txm o 52 h7 superspeed transmit minus ds2_dp i/o 76 a6 usb 2.0 data plus ds2_dm i/o 77 a5 usb 2.0 data minus ds2_ovrcurr i 1 b1 overcurrent detect input for ds2 port ds2_pwren [7] i/o 86 b2 vbus power enable output for ds2 port. when the port is disable d, this pin is in tristate. ds2_cdp_en [8] this pin is called ds2_cdp_en in the pin-strap configuration mo de. ds2_amber [7] i/o 5 e4 led_amber output for ds2 port non_removable[0] [8] this pin is called non_removable[0] in the pin-strap configurat ion mode. ds2_green [7] i/o 6 e3 cyusb3312/3314/3324: led_green output for ds2 port ds2_vbusen_sl [7] cyusb3326/3328: vbus power en able output for ss port 2 non_removable[1] [8] this pin is called non_removable[1] in the pin-strap configurat ion mode. ds2_led_ss [7] i/o 84 c3 led_ss output for ds2 port pwr_en_sel [8] this pin is called pwr_en_sel in the pin-strap configuration mo de. ds3 port nc ds3_rxp i 45 k10 superspeed receive plus nc ds3_rxm i 46 j10 superspeed receive minus nc ds3_txp o 48 k7 superspeed transmit plus nc ds3_txm o 49 k8 superspeed transmit minus nc ds3_dp i/o 79 c4 usb 2.0 data plus nc ds3_dm i/o 78 c5 usb 2.0 data minus ds3_ovrcurr i 65 b7 cyusb3314/3324/3326/3328: overcu rrent detect input for ds3 port cyusb3312: this pin must be pulled high using a 10 k ? to vdd_io. ds3_pwren [7] i/o 87 a1 vbus power enable output for ds3 port. when the port is disable d, this pin is in tristate. ds3_cdp_en [8] this pin is called ds3_cdp_en in the pin-strap configuration mo de. ds3_amber [7] i/o 85 b3 led_amber output for ds3 port vid_sel[2] [8] this pin is called vid_sel[2] in the pin-strap configuration mo de. table 4. 88-pin qfn, 100-ball b ga pinout for cyusb331x and cyu sb332x (continued) pin name type pin# ball# description cyusb3312 cyusb3314 cyusb3324 cyusb3326 cyusb3328 notes 7. this pin can be configured as a gpio using custom firmware. f or information contact www.cypress.com/support . 8. for pin-strap configuration details, refer to ta b l e 6 on page 25 .
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 22 of 43 ds3_green [9] i/o 64 b8 cyusb3312/3314/3324: led_green output for ds3 port ds3_vbusen_sl [9] cyusb3328: vbus power enabl e output for ss port 3 vid_sel[1] [10] this pin is called vid_sel[1] in the pin-strap configuration mo de. for pin-strap configuration details, refer to table 6 on page 25 . ds3_led_ss [9] i/o 63 b9 led_ss output for ds3 port pin_strap [10] this pin is called pin_ strap in pin-strap configuration mode. w hen connected to vdd_io through a 10-k ? resistor, this pin enables pin-strap configurat ion mode for hx3. ds4 port nc ds4_rxp i 20 k4 superspeed receive plus nc ds4_rxm i 19 k5 superspeed receive minus nc ds4_txp o 16 k1 superspeed transmit plus nc ds4_txm o 17 k2 superspeed transmit minus nc ds4_dp i/o 81 a3 usb 2.0 data plus nc ds4_dm i/o 82 a2 usb 2.0 data minus ds4_ovrcurr i 36 f6 cyusb3314/3324/3326/3328: overcu rrent detect input for ds4 port . cyusb3312: this pin must be pulled high using a 10 k ? to vdd_io. ds4_pwren/pwr_en4 i/o 35 g7 vbus power enable output for ds4 port. this pin is also used as power enable output when configured in ganged power mode using the bl aster plus tool. when the port is disa bled, this pin is in tristate. ds4_cdp_en [10] this pin is called ds4_cdp_en in the pin-strap configuration mo de. ds4_amber [9] i/o 30 j4 led_amber output for ds4 port i2c_dev_id [10] this pin is called i2c_dev_id in the pin-strap c onfiguration mo de. ds4_green [9] i/o 43 h9 cyusb3312/3314/3324: led_green output for ds4 port ds4_vbusen_sl cyusb3328: vbus power enable output for ss port 4 vid_sel[0] [10] this pin is called vid_sel[0] in the pin-strap configuration mo de. ds4_led_ss i/o 26 h4 led_ss output for ds4 port. the l ed must be conn ected to gnd as shown in figure 16 on page 25 . if led is not used, this pin must be pulled high using a 10 k ? to vdd_io. reserved1 i 27 g4 this pin must be pulled high u sing a 10 k ? to vdd_io. mode select, clock, and reset mode_sel[0] i 28 g5 device operati on mode select b it 0; refer to table 5 on page 24 mode_sel[1] i 29 f4 device operati on mode select b it 1; refer to table 5 on page 24 xtl_out a 68 e6 crystal out xtl_in a 69 e5 crystal in resetn i 37 f7 active low reset input i2c_clk i/o 40 j6 i 2 c clock i2c_data i/o 41 g8 i 2 c data table 4. 88-pin qfn, 100-ball b ga pinout for cyusb331x and cyu sb332x (continued) pin name type pin# ball# description cyusb3312 cyusb3314 cyusb3324 cyusb3326 cyusb3328 notes 9. this pin can be configured as a gpio using custom firmware. f or information contact www.cypress.com/support . 10. for pin-strap configuration details, refer to ta b l e 6 on page 25 .
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 23 of 43 suspend i/o 25 g3 hub suspend status indicator. th is pin is assert ed if both the ss and usb 2.0 hubs are in the suspen d state and is de-asserted when e ither of the hubs comes out of the suspend state. power and ground vdd_efuse pwr 24 h3 1.2 v normal operation, 2.5 v for programming. customers should connect to 1.2 v avdd12 pwr 15, 21, 44, 56, 62, 67 a10, c9, f9, h1, h10, j2 1.2 v analog supply gnd pwr 50 b5, c6, d5, d7, d9, e9, f2, g9, h6, j1, j3, j9 gnd pin dvdd12 pwr 8, 12, 18, 33, 47, 53, 59, 83 b10, d4, d6, d8, e1, e10, f5, k3, k9 1.2 v core supply vbus _us pwr 22 h2 cyusb3324/3328: connect the vbus_ us pin to the local 5 v supply . if aca-dock mode is disabled using configuration options on page 24 , this pin must be connect ed to vbus from us port. other part numbers: this pin must be connected to vbus from us port. vbus_ds pwr 23 g2 this pin is used to power the apple-charging circuit in hx3. for bc v1.2 compliance testing, connect pin to gnd. for normal operation, connect pin to local 5 v supply. avdd33 pwr 9, 70, 75, 80 a4, a7, b6, f3 3.3 v analog supply vdd_io pwr 34, 66, 88 b4, e7, g6 3.3 v i/o supply usb precision resistors rref_usb2 a 7 e2 connect pin to a precision resistor (6.04 k ? 1%) to generate a current reference for usb 2.0 phy. rref_ss a 32 h5 connect pin to a precision resistor (200 ? 1%) for ss phy termination impedance calibration. table 4. 88-pin qfn, 100-ball b ga pinout for cyusb331x and cyu sb332x (continued) pin name type pin# ball# description cyusb3312 cyusb3314 cyusb3324 cyusb3326 cyusb3328
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 24 of 43 system interfaces upstream port (us) this port is compliant with the usb 3.0 specification and inclu des an integrated 1.5 k ? pull-up and termination resistors. it also supports aca-dock to enable charging an otg host connected on the us port. downstream ports (ds1, 2, 3, 4) ds ports are compliant with the usb 3.0 specification and integrate 15 k ? pull-down and termination resistors. ports can be disabled or enabled, and can be set to removable or non-removable options. bc v1.2 charging is enabled by default and can be disabled on each ds port using the configuration options (see configuration options ). communication interfaces (i 2 c) the interface follows the inter-ic bus specification, version 3 .0, with support for the standard mode (100 khz) and the fast mode (400 khz) frequencies. hx3 supports i 2 c in the slave and master modes. the i 2 c interface supports the multi-master mode of operation. both the scl and sda signals require external pull-up resistors based on the specification. vdd_io for hx3 is 3.3 v and it is expected that the i 2 c pull-up resistors will be connected to the same supply. oscillator hx3 requires an external crystal with a frequency of 26 mhz and an accuracy of 150 ppm in parallel resonant, fundamental mode. the crystal drive circuit i s capable of a low-power drive level (<200 w). the crystal connection to the xtl_out and xtl_in pins is shown in figure 14 . figure 14. crystal connection gpios hx3 gpios are used for overc urrent sensing, controlling external power switches, and driving leds. these pins can sink up to 4 ma current each. gpios also enable pin-straps for input configuration. refer to table 6 for more details. power control the pwr_en[1-4] and ov_curr[1-4] pins interface hx3 to external power switches. these pins are used to control power switches for ds port power and monitor overcurrent conditions. the power switch polarity and the power control mode (individua l and ganged) can be changed usin g the configuration options. reset hx3 operates with two external power supplies, 3.3 v and 1.2 v. there is no power sequencing requirement between these two supplies. however, the resetn pin should be held low until both these supplies become stable. the resetn pin can be tied t o vdd_io through an external resistor and to ground (gnd) through an external capacitor (minimum 5 ms time constant), as shown in figure 15 . this creates a clean reset signa l for power-on reset (por). hx3 does not support internal brown-out detection. if the syste m requires this feature, an external reset should be provided on the resetn pin when supplies are below their valid operating ranges. figure 15. reset connection configuration mode select configuration options are selected through the mode_sel pins and the pin-strap enable pin (pin_strap). after power-up, these pins are sampled by an on-chip bootloader to determine the configuration options (see ta b l e 5 ). configuration options hx3 can be configured by u sing one of the following: efuse (one-time programmable memory) pin-strap (read configuration from dedicated pins at power on) external i 2 c slave such as an eeprom external i 2 c master the i 2 c master/slave configuration overrides the pin-strap configuration. pin-straps overri de the efuse configuration, and the efuse configuration overrides the internal rom configuration. efuse configuration hx3 contains efuses, which are otp elements on the chip that can be electrically blown. the efuses are read by the bootloade r to determine the customer-spec ific configurations. efuse programming is supported only at factory and distributor locations where programming conditions can be controlled. efuse programming is supported under the following conditions: 10 pf 10 pf 26 mhz xtl_out xtl_in table 5. hx3 boot sequence mode sel[1] mode sel[0] hx3 configuration modes 0 0 reserved. do not use this mode. 1 1 internal rom configuration 01 i 2 c master, read configuration from i 2 c eeprom * 10 i 2 c slave, configure from an external i 2 c master * * download cypress-provided firmware from www.cypress.com/hx3. resetn vdd_io 1.5 f 10 k ?
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 25 of 43 temperature range of 25 cC70 c and programming voltage of 2.5 vC2.7 v. pin-strap configuration pin-straps are supported for select product options (see table 1 on page 5 ) to provide reconfigurability without an additional eeprom. the pin-strap configuration is enabled by pulling the pin #63 of 88-pin qfn high. ta b l e 6 on page 25 shows the configuration options supported through pin-straps and the gpios used for this purpose. figure 16 and figure 17 show how the gpios need to be connected if pin-strap and led connection are required or only pi n-strap is required. hx3 samples pin-strap gpios at power-up. floating straps are considered as invalid and the def ault configuration is used. if pin_strap (pin #63 of 88-pin qfn) is floating, all strap inputs are considered invalid. a gpio is considered strapped 1 or 0 when connected with a weak pull-up (10 k ? ) or pull-down (10 k ? ) respectively. after the initial sampling at power-up and reset, the gpios are used in their normal functions. figure 16. pin-strap with led or led-only connection figure 17. pin-strap connection vdd_io to gpio 800 ? C 1 k ? 800 ? C 1 k ? vss to gpio 10 k ? 10 k ? pin-strap high with led pin-strap low with led to gpio vdd_io 10 k ? 10 k ? to gpio vss pin-strap high pin-strap low notes 11. see figure 16 and figure 17 . 12. i2c_dev_id is valid only when hx3 is in i 2 c slave mode. 13. vid, port_disable, non_removable are group straps. if one of the pins in a group strap is floating (invalid), that group in put will be invalid and the default will not be overwritten. 14. these ds ports are exposed ports and the connected devices c an be removed. 15. dsx_cdp_en will be active low input when pwr_sw_pol is set t o active low; similarly dsx_cdp_en will be active high input wh en pwr_sw_pol is set to active high. table 6. pin-strap configuration 88-qfn pin # pin-strap name strapped 0 [11] strapped 1 [11] 30 i2c_dev_id [12] id 0: hx3 i 2 c slave address (7 bits) is 0x60. this is also the default i 2 c slave address for the 68-pin qfn package. id 1: hx3 i 2 c slave address (7 bits) is 0x58 31 pwr_sw_pol power enable and overcurrent will be active low power enable and overcu rrent will be active high 2 aca_dock disabled enabled 84 pwr_en_sel individual gang 63 pin_strap [13] no pin-strapping pin-strapping configuration enabled 4 port_disable[1] port_disable[1:0] = b00: ds1, ds2, ds3, ds4 active b01: ds1, ds2, ds3 active b10: ds1, ds2 active b11: ds1 active pin-straps cannot enable ports d isabled by factory setting. 3 port_disable[0] 6 non_removable[1] [14] non_removable[1:0] = b00: ds1, ds2, ds3, ds4 removable b01: ds1, ds2, ds3 removable b10: ds1, ds2 removable b11: ds1 removable 5 non_removable[0] [14] 85 vid[2] reserved. if pin_str ap is enabled and cy vid is required, strap vid[2:0] to 1. 64 vid[1] 43 vid[0] 38 ds1_cdp_en [15] strapped 0 strapped 1 strapped 0 strapped 1 ds1 cdp enabled ds1 cdp disabled ds 1 cdp disabled ds1 cdp enabled 86 ds2_cdp_en [15] ds2 cdp enabled ds2 cdp disabled ds 2 cdp disabled ds2 cdp enabled 87 ds3_cdp_en [15] ds3 cdp enabled ds3 cdp disabled ds 3 cdp disabled ds3 cdp enabled 35 ds4_cdp_en [15] ds4 cdp enabled ds4 cdp disabled ds 4 cdp disabled ds4 cdp enabled
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 26 of 43 i 2 c configuration when enabled for i 2 c configuration through the mode_sel pins (see ta b l e 5 on page 24 ), hx3 can be configured as an i 2 c master or as an i 2 c slave. hx3s configuration data is a maximum of 197 bytes and hx3 s firmware is 10 kb. note that hx3s firmware also incl udes configuration settings. hx3 as i 2 c master hx3 reads configurations from an external i 2 c eeprom with sizes ranging from 16 to 64 kb. an example of a supported eeprom is 24lc128. based on t he contents of t he bsignature and bimagetype fields in ta b l e 7 on page 26 , hx3 performs one of the following actions: loads custom configuration settings from the eeprom when bsignature is cy and bimagetype is 0xd4. loads the cypress-provided firmware from the eeprom when bsignature is cy and bimagetype is 0xb0. this firmware also includes configuration settings. if bsignature ? cy, hx3 enumerates i n the vendor-specific mode. the contents of the eeprom can be updated with the easy-to-use cypress blaster plus tool. blaster plus is a gui-based tool to configure hx3. this tool allows to do the following: download the cypress-provided firmware from a pc via hx3's us port and store it on an eeprom con nected to hx3s i 2 c port. read the configurat ion settings from the eeprom. these settings are displayed in the blaster plus gui. modify settings as required. write back the updated settings on to the eeprom. in addition, an image file can be creat ed for external use. the blaster plus tool, user guide, and the cypress-provided firmware are available at www.cypress.com/hx3 . hx3 as i 2 c slave an external i 2 c master can program the configuration settings into hx3 according to the eeprom map in ta b l e 7 on page 26 . alternatively, the hx3 firmware (<10 kb), which includes config - uration settings, can also be programmed. it is recommended to use the blaster plus tool to create the hx3 firmware or configu- ration image file. hx3s i 2 c slave address needs to be provided while creating the image file. refer to ta b l e 6 for hx3s i 2 c slave address. table 7. eeprom map i 2 c offset bits name default description 0 7:0 bsignature lsb (c) 0x43 the first byte of the 2-byte signat ure initialized with cy ascii text. when the signature is not vali d, the hub enumerates as a vendor-specific device. 1 7:0 bsignature msb (y) 0x59 the second byte of the 2-byte signa ture initialized with cy ascii text. when the signature is not valid, the hub enumerates as a vendor-specific device. 2 7:6 bimagectl b00 reserved 5:4 i 2 c speed b11 b01: 400 khz b11: 100 khz 3:1 bimagectl b000 reserved 0 bimagectl 0 0: execution binary file 1: data file 3 7:0 bimagetype 0xd4 0xd4: load only configuration 0xb0: load firmware boot image all other bimage type will return an error code. 4 7:0 bd4length 40 bd4length is defined in bytes as the length from offset 5. i 2 c offset bytes 0C4 are the header bytes. bd4length = 6: only upd ate vid, pid, and did bd4length = 18: configura tion options (no phy trim) bd4length = 40: configuration options with phy trim options bd4length > 40: user must pro vide valid string descriptors bd4length > 192: error 5 7:0 vid [7:0] 0xb4 custom vendor id - lsb 6 7:0 vid [15:8] 0x04 custom vendor id - msb 7 7:0 pid [7:0] 0x04 custom product id (pid) default: 0x6504 if separate pid is used for usb 2.0, the usb 2.0 pid will be re ad from offset 35 and 36. else, usb 2.0 pid = pid+2; default: 0x6506 8 7:0 pid [15:8] 0x65
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 27 of 43 9 7:0 did [7:0] 00 - 88-pin qfn, 10 - 68-pin qfn custom device id - revision - lsb 10 7:0 did [15:8] 50 custom de vice id - revision - msb 11 7:0 reserved 0 reserved 12 7:4 shared_link_en b0000 e nable shared link on ds port bit[7:4]=ds4, ds3, ds2, ds1 0: shared link not enabled 1: shared link enabled 3:0 shc_active_ports [3:0] b1111 indicates if a superspeed port i s active. bit[3:0] = ds4, ds3, ds2, ds1 0: not active 1: active 13 7:0 power_on_time 0x32 time (in 2 -ms intervals) from the time th e power-on sequence begins on a port until power is good on that port (bpwron2pwrgood) 14 7:4 removable_ports [3:0] b1111 i ndicates if the port is remova ble. bit[7:4]=ds4, ds3, ds2, ds1 0: non-removable 1: removable 3:0 uhc_active_ports [3:0] b1111 i ndicates if a usb 2.0 port is a ctive. bit[3:0]=ds4, ds3, ds2, ds1 0: not active 1: active 15 7 ss_led_pin_control 0 po rt 1C4: ss led disable 0: ds[1:4]_led_ss are leds. the led glows when the ss port is active and not in disabled state. 1: ds[1:4]_led_ss are not leds 6 green_led_pin_control 0 port 1 C4: usb 2.0 green led disable 0: ds[1:4]_green are leds 1: ds[1:4]_green are not leds 5 amber_led_pin_control 0 port 1 C4: usb 2.0 amber led disable 0: ds[1:4]_amber are leds 1: ds[1:4]_amber are not leds 4 port_indicators 1 port indicators supported 0: port indicators are not suppo rted on its ds-facing ports and the usb 2.0 port_indicato r request has no effect. 1: port indicators are supported on its ds-facing ports and the usb 2.0 port_indica tor request controls the indicators. 3 compound_hub 0 identifie s a compound device. 0: hub is not part of a compound device. 1: hub is part of a compound device. 2:1 reserved 0 reserved 0 gang 0 1: ganged power switch enable for all ds ports 0: individual port power swi tch enable for each ds port table 7. eeprom map (continued) i 2 c offset bits name default description
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 28 of 43 16 7 suspend_indicator_disable 0 0: suspend indicator enabled 1: suspend indicator disabled 6 ss_us_disable 0 hub mode of operation (usb 3.0 or usb 2.0) 0: usb 3.0 hub and usb 2.0 hub enabled 1: usb 3.0 hub disabled and usb 2.0 hub enabled 5 pwr_en_polarity 0 power swit ch control output polarity 0: active low 1: active high 4:0 port_polarity b00000 usb 2.0 dp and dm swapped bit[4:0]=ds4, ds3, ds2, ds1, us 1: port polarity swapped 0: port polarity not swapped 17 7:5 reserved 0 reserved 4 bc_enable 1 0: bc v1.2 disabled 1: bc v1.2 enabled 3 aca_dock 0 if this bit is set, e nable aca-dock on the us port 2 apple_xa 0 0: max limit fo r apple charging 2.1 a 1: max limit for apple charging 1 a 1 reserved 0 reserved 0 ghost_charge_en 1 0: ghost charging disabled 1: ghost charging enabled 18 7:4 cdp_en[3:0] b1111 per-port charging setting bit[7:4]=ds4, ds3, ds2, ds1 0: cdp disabled 1: cdp enabled 3:0 dcp_en[3:0] b0000 per-port charging setting bit[3:0]=ds4, ds3, ds2, ds1 0: dcp disabled 1: dcp enabled 19 7 embedded_hub 0 if this bit is set, the us is as an embedded po rt and vbus connected to vbus_us pin is ignored. 6 illegal_descriptor 1 if this bit is set, the usb 2.0 hub control ler will accept both 0x00 and 0x29 as valid descriptor ty pes. if '0', only 0x29 will be accepted as a valid descriptor type. 5 reserved 1 reserved 4 oc_polarity 0 overcu rrent input polarity 0: active low 1: active high 3:0 oc_timer b1000 time in millisec onds for which the overcurrent inputs will be filtered 20 7:0 reserved 0 reserved 21 7:4 reserved 0 reserved 3 string_descriptor_enable [16] 0 0: string descriptor support is disabled 1: string descriptor support is enabled when string descriptors are not supported, the hub controller returns a non-zero index (compile-time programmable) for each string which is supported, and 0x00 for each string not supported, as indicated by this field. 2:0 reserved 0 reserved 22 7:0 reserved 0 reserved note 16. when the string descriptor supports langid, manufacturer, pr oduct and serial number, the serial number must be unique for e ach device. table 7. eeprom map (continued) i 2 c offset bits name default description
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 29 of 43 23 7:6 hs_amplitude_ds4 b00 hs driver amplitude control; hs driver current: +0% to +7.5% b00: default b01: +2.5% b10: +5% b11: +7.5% 5:4 hs_amplitude_ds3 b00 3:2 hs_amplitude_ds2 b00 1:0 hs_amplitude_ds2 b00 24 7:6 hs_amplitude_us b00 5:2 hs_slope b'0100 hs driver slope control for all ports b0000: +15% b0001: +5% b0100: default b0101: -5% b1111: -7.5% 1:0 hs_tx_vref b10 reference vol tage for hs squelch (transmission envelope detector) for all ports b00: 96 mv b01: 108 mv b10: 120 mv b11: 132 mv 25 7:3 hs_preemp_en[4:0] b00000 hs d river pre-emphasis enable C fo r ports ds4, ds3, ds2, ds1, and us 0: pre-emphasis is disabled 1: pre-emphasis is enabled 2 hs_preemp_depth_ds4 [17] 0 hs driver pre-emphasis depth 0: +10% 1: +20% 1 hs_preemp_depth_ds3 [17] 0 0 hs_preemp_depth_ds2 [17] 0 26 7 hs_preemp_depth_ds1 [17] 0 6 hs_preemp_depth_us [17] 0 5 reserved 1 reserved 4:1 pcs_tx_deemph_ds4 0x6 usb 3. 0 tx driver de-emphasis value 0x3: -2.75 db 0x6: -3.4 db (default) 0x9: -4.0 db 0 reserved 0 reserved 27 7:4 pcs_tx_deemph_ds3 0x6 usb 3. 0 tx driver de-emphasis value 0x3: -2.75 db 0x6: -3.4 db (default) 0x9: -4.0 db 3:0 pcs_tx_deemph_ds2 0x6 28 7:4 pcs_tx_deemph_ds1 0x6 3:0 pcs_tx_deemph_us 0x6 29 7 reserved 0 reserved 6 reserved 1 reserved 5:0 pcs_tx_swing_full_ds4 0x29 adjus t launch amplitude of the tran smitter 0x1f C 0.9 v 0x29 C 1.0 v (default) 0x35 C 1.1 v 0x3f C 1.2 v 30 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds3 0x29 adjus t launch amplitude of the tran smitter 0x1f C 0.9 v 0x29 C 1.0 v (default) 0x35 C 1.1 v 0x3f C 1.2 v table 7. eeprom map (continued) i 2 c offset bits name default description note 17. hs_preemp_depth is valid only when corresponding hs_preemp_e n is set for that port.
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 30 of 43 31 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds2 0x29 adjus t launch amplitude of the tran smitter 0x1f C 0.9 v 0x29 C 1.0 v (default) 0x35 C 1.1 v 0x3f C 1.2 v 32 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds1 0x29 adjus t launch amplitude of the tran smitter 0x1f C 0.9 v 0x29 C 1.0 v (default) 0x35 C 1.1 v 0x3f C 1.2 v 33 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_us 0x29 adjust launch amplitu de of the trans mitter 0x1f C 0.9 v 0x29 C 1.0 v (default) 0x35 C 1.1 v 0x3f C 1.2 v 34 7:0 reserved 0 reserved 35 7:0 uhc_pid [7:0]_lsb 0x06 u sb 2.0 pid. if bd4length ? 40, usb 2.0 pid will be read from this location. 36 7:0 uhc_pid [15:8]_msb 0x65 37C44 7:0 reserved 0 eight bytes reserved for future expansion 45 7:0 blength: langid 4 size of langid (defined by spec as n+2) 46 7:0 desctype 3 string descr iptor type (constant value) 47 7:0 langid - msb 9 string language id - msb of wlangid 48 7:0 langid - lsb 4 string language id - msb of wlangid 49 7:0 blength: manufacturer (x) 54 m anufacturer string length (bl ength: langid + blength: manufacturer + blength: produc t + blength: serial number should be less than or eq ual to 152 bytes). x 66. 50 7:0 desctype 3 string descr iptor type (constant value) 51 7:0 bstring: manufacturer 2, 0, 0, 0, 1, 0, 4, 0, , 0, c, 0, y, 0, p, 0, r, 0, e, 0, s, 0, s, 0, , 0, s, 0, e, 0, m, 0, i, 0, c, 0, o, 0, n, 0, d, 0, u, 0, c, 0, t, 0, o, 0, r, 0 manufacturer string: unicode u tf-16le per usb 2.0 specifi- cation : 2014 cypress semiconductor 49 + x 7:0 blength: product (y) 22 pr oduct string length (blength: langid + blength: manufac- turer + blength: pro duct + blength: seri al number should be less than or equal to 152 bytes). y 66. 50 + x 7:0 desctype 3 string de scriptor type (constant value) table 7. eeprom map (continued) i 2 c offset bits name default description
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 31 of 43 emi hx3 meets the emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consum er electronics. hx3 tolerates emi conducted by aggressors outlined by the above specifica- tions and continues to function as expected. esd hx3 has a built-in esd protection on all pins. the esd protecti on level provided on these ports is 2.2 kv human body model (hbm) based on the jesd22-a114 specification. 51 + x 7:0 bstring: product c, 0, y, 0, -, 0, h, 0, x, 0, 3, 0, , 0, h, 0, u, 0, b, 0 product string: unicode utf-16l e per usb 2.0 specification: cy-hx3 hub 49 + x + y 7:0 blength: serial num ber (z) 22 serial number string l ength (blength: langid + blength: manufacturer + blength: produc t + blength: serial number should be less than or eq ual to 152 bytes). z 66. 50 + x + y 7:0 desctype 3 string descriptor type (constant value) 51 + x + y 7:0 bstring: serial number 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0, 8, 0, 9, 0, a, 0 serial number string: unicode utf-16le per usb 2.0 speci- fication: 123456789a table 7. eeprom map (continued) i 2 c offset bits name default description
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 32 of 43 absolute maximum ratings exceeding maximum ra tings may shorten t he useful life of the device. user guidelines are not tested. storage temperature................................... C65 c t o +150 c operating temperature .............................. C40 c to + 85 c electrostatic discharge voltage ............................... .. 2200 v oscillator or crystal frequency ................. 26 mhz 150 pp m i/o voltage supply ............................................ ...3 v to 3.6 v maximum input sink current per i/o ............................ .. 4 ma electrical specifications hx3 meets all usb-if electrical compliance specifications. dc electrical characteristics table 8. dc electrical characteristics parameter description conditions min typ max units dvdd12 1.2 v core supply C 1.14 1.2 1.26 v vdd_efuse efuse supply normal operation 1.14 1.2 1.26 v programming 2.5 2.6 2.7 v avdd12 1.2 v analog supply C 1.14 1.2 1.26 v vdd_io 3.3 v i/o supply C 3 3.3 3.6 v avdd33 3.3 v analog supply C 3 3.3 3.6 v v ih input high voltage C 0.7 vdd_io C vdd_io v v il input low voltage C 0 C 0.3 vdd_io v v oh output high voltage output high voltage at i oh ? +4 ma 2.4 C C v v ol output low voltage output low voltage at i ol ? ? C4 ma C C 0.4 v i os input sink current led gpio usage C C 4 ma i ix input leakage current all i/o signals held at vdd_io or gnd C1 C 1 a i oz output hi-z leakage current C C C 10 a i cc 1.2 v supplies combined operating current C C 410 526 ma i cc 3.3 v supplies combined operating current C C 260 286 ma v ramp voltage ramp rate on core and i/o supplies voltage ramp must be monotonic 0.2 C 50 v/ms v n noise level permitted on core and i/o supplies max p-p noise level permitted on all supplies except avdd C C 100 mv v n_usb noise level permitted on avdd12 and avdd33 supply max p-p noise level permitted usb supply C C 20 mv
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 33 of 43 power consumption ta b l e 9 provides the power consumption estimates for hx3 under differe nt conditions. ta b l e 1 0 summarizes the power consumption for various combinations of dev ices connected to ds ports. for example, to calculate the hx3 power consumption for three s s devices connected to ds ports (and no device connected to one ds port), and a us port co nnected to a usb 3.0 host: power consumption = [a] + 2*[ g] = 492.5 + 2*76 = 644 mw [a] is the active powe r consumption for the us port connected t o a usb 3.0 host and the ss device connect ed to the ds port. [g] is the incremental power con sumption for an additional ss d evice connected to the ds port. table 9. power consumption esti mates for variou s usage scenari os device condition number and speed of ds ports connected typical consumption comments supply current (ma) power (mw) 1.2 v 3.3 v suspend [18] na 12.0 7.1 37.8 C active power with usb 3.0 host [19] 1 ss 204.1 75.0 492.5 [a] 1 hs 51.2 45.2 210.7 [b] 1 fs 51.2 34.0 173.7 [c] 1 ss + 1 hs 218.0 103.4 602.9 [d] active power with usb 2.0 host [19, 20] 1 hs 51.2 45.2 210.7 [e] 1 fs 51.2 34.0 173.7 [f] incremental active power for additional ds port ss 39.4 8.7 76.0 [g] hs 7.0 19.8 73.7 [h] fs 7.0 14.2 55.2 [i] active power saving per disabled ds port [21] C 10.6 9.6 44.4 [j] table 10. power consumption under various configurations configuration number of ds devices connected with data transfer typical consumption comments supply current (ma) power (mw) 1.2 v 3.3 v usb 3.0 4-port hub (usb 3.0 host) 4 ss devices 322 101 720 [a] + 3*[g] 3 ss + 1 hs devices 297 121 755 [d] + 2*[g] 3 ss devices 283 92 644 [a] + 2*[g] usb 3.0 4-port hub with one port disabled (usb 3.0 host) 3 ss devices 272 83 600 [a] + 2*[g] - [j] 2 ss + 1 hs devices 247 103 634 [d] + [g] - [j] shared link with eigh t ds ports 4 ss + 4 h s devices 357 189 1052 [d ] + 3*([g] + [h]) usb 2.0 4-port hub (usb 2.0 host) 4 hs devices 72 105 432 [e] + 3*[h] 3 hs + 1 fs devices 72 99 413 [e] + 2*[h] + [i] notes 18. us port in low-power state (ss in u3 and usb 2.0 in l2). 19. all four ds ports are enabled. 20. us ss disabled using configuration options. refer to table 7 on page 26 for i 2 c configuration options. 21. power saving applicable only with a usb 3.0 host. ds ports c an be disabled through configuration options. refer to table 6 on page 25 for pin-strapping and table 7 on page 26 for i 2 c configuration options.
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 34 of 43 ordering information ta b l e 11 lists hx3s ordering information. the table contains only the part numbers that are currently available for order. additional part numbers for industrial temperature range can be made avail able on request. for more information, visit the cypress website or contact the local sales representative. table 11. ordering information serial no. ordering part number number of ds ports number of shared link ports ghost charge aca- dock temperature package 1. CYUSB3302-68LTXC 2 (usb 3.0) 0 yes no 0 cC70 c 68-pin qfn 2. cyusb3302-68ltxi 2 (usb 3.0) 0 yes no C40 cC85 c 68-pin qfn 3. cyusb3304-68ltxc 4 (usb 3.0) 0 yes no 0 cC70 c 68-pin qfn 4. cyusb3304-68ltxi 4 (usb 3.0) 0 yes no C40 cC85 c 68-pin qfn 5. cyusb3312-88ltxc 2 (usb 3.0) 0 yes no 0 cC70 c 88-pin qfn 6. cyusb3312-88ltxct 2 (usb 3.0) 0 yes no 0 cC70 c 88-pin qfn 7. cyusb3312-88ltxi 2 (usb 3.0) 0 yes no C40 cC85 c 88-pin qfn 8. cyusb3312-88ltxit 2 (usb 3.0) 0 yes no C40 cC85 c 88-pin qfn 9. cyusb3314-88ltxc 4 (usb 3.0) 0 yes no 0 cC70 c 88-pin qfn 10. cyusb3314-88ltxct 4 (usb 3.0) 0 yes no 0 cC70 c 88-pin qfn 11. cyusb3314-88ltxi 4 (usb 3.0) 0 yes no C40 cC85 c 88-pin qfn 12. cyusb3314-88ltxit 4 (usb 3.0) 0 yes no C40 cC85 c 88-pin qfn 13. cyusb3324-88ltxc 4 (usb 3.0) 0 yes yes 0 cC70 c 88-pin qfn 14. cyusb3324-88ltxct 4 (usb 3.0) 0 yes yes 0 cC70 c 88-pin qfn 15. cyusb3324-88ltxi 4 (usb 3.0) 0 yes yes C40 cC85 c 88-pin qfn 16. cyusb3324-88ltxit 4 (usb 3.0) 0 yes yes C40 cC85 c 88-pin qfn 17. cyusb3326-88ltxc 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no 0 cC70 c 88-pin qfn 18. cyusb3326-88ltxct 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no 0 cC70 c 88-pin qfn 19. cyusb3326-88ltxi 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no C40 cC85 c 88-pin qfn 20. cyusb3326-88ltxit 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no C40 cC85 c 88-pin qfn 21. cyusb3328-88ltxc 8 (4 ss, 4 usb 2.0) 4 yes yes 0 cC70 c 88-pin qfn 22. cyusb3328-88ltxct 8 (4 ss, 4 usb 2.0) 4 yes yes 0 cC70 c 88-pin qfn 23. cyusb3328-88ltxi 8 (4 ss, 4 usb 2.0) 4 yes yes C40 cC85 c 88-pin qfn 24. cyusb3328-88ltxit 8 (4 ss, 4 usb 2.0) 4 yes yes C40 cC85 c 88-pin qfn 25. cyusb3302-bvxc 2 (usb 3.0) 0 yes no 0 cC70 c 100-ball bga 26. cyusb3302-bvxi 2 (usb 3.0) 0 yes no C40-85 c 100-ball bga 27. cyusb3304-bvxc 4 (usb 3.0) 0 yes no 0 cC70 c 100-ball bga 28. cyusb3304-bvxi 4 (usb 3.0) 0 yes no C40 cC85 c 100-ball bga 29. cyusb3312-bvxc 2 (usb 3.0) 0 yes no 0 cC70 c 100-ball bga 30. cyusb3312-bvxi 2 (usb 3.0) 0 yes no C40 cC85 c 100-ball bga 31. cyusb3314-bvxc 4 (usb 3.0) 0 yes no 0 cC70 c 100-ball bga 32. cyusb3314-bvxi 4 (usb 3.0) 0 yes no C40 cC85 c 100-ball bga 33. cyusb3324-bvxc 4 (usb 3.0) 0 yes yes 0 cC70 c 100-ball bga 34. cyusb3324-bvxi 4 (usb 3.0) 0 yes yes C40 cC85 c 100-ball bga
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 35 of 43 ordering code definitions 35. cyusb3326-bvxc 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no 0 cC70 c 100-ball bga 36. cyusb3326-bvxi 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no C40 cC85 c 100-ball bga 37. cyusb3328-bvxc 8 (4 ss, 4 usb 2.0) 4 yes yes 0 cC70 c 100-ball bga 38. cyusb2302-68ltxi 2 (usb 2.0) 0 yes no C40 cC85 c 68-pin qfn 39. cyusb2304-68ltxi 4 (usb 2.0) 0 yes no C40 cC85 c 68-pin qfn table 11. ordering information (continued) serial no. ordering part number number of ds ports number of shared link ports ghost charge aca- dock temperature package usb cy x x - xxxx x x x 3 x = blank or t blank = tube; t = tape and reel temperature range: x = c or i c= commercial; i= industrial pb-free package type: xxxx = 68lt or 88lt or bv 68lt = 68-pin qfn 88lt = 88-pin qfn bv = 100-ball bga number of ports feature list: x = 0 or 1 or 2 0 = basic, 1 = interm ediate, 2 = advanced hub family usb speed: x = 3 or 2 3 = usb 3.0; 2 = usb 2.0 marketing code: usb company id: cy = cypress x
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 36 of 43 packaging table 12. package characteristics parameter description min typ max units t a operating ambient temperature C40 C 85 c t j operating junction temperature C40 C 125 c t ja package j a (68-pin qfn) C 16.2 C c/w t ja package j a (88-pin qfn) C 15.7 C c/w t ja package j a (100-ball bga) C 35 C c/w t jc package j c (68-pin qfn) C 23.8 C c/w t jc package j c (88-pin qfn) C 18.9 C c/w t jc package j c (100-ball bga) C 12 C c/w table 13. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 68-pin qfn 260 c 30 seconds 88-pin qfn 260 c 30 seconds 100-ball bga 260 c 30 seconds table 14. package moisture sens itivity level (msl), ipc/jedec j-std-2 package msl 68-pin qfn msl 3 88-pin qfn msl 3 100-ball bga msl 3
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 37 of 43 package diagrams figure 18. 68-pin qfn (8 8 1.0 mm) lt68b 5.1 5.1 mm epad (sawn) package outline figure 19. 88-pin qfn (10 10 1.0 mm) lt88b 5.3 5.3 epad (sawn) package outline 1. hatch area is solderable exposed pad 2. reference jedec#: mo-220 3. all dimensions are in millimeters notes: 001-78925 *b 001-76569 *b
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 38 of 43 figure 20. 100-ball bga (6.0 6.0 1.0 mm) bz1 00 package out line n is the number of populated solder ball positions for matrix when there is an even number of solder balls in the outer row, when there is an odd number of solder balls in the outer row define the position of the center solder ball in the outer row. "sd" and "se" are measured with respect to datums a and b and symbol "me" is the ball matrix size in the "e" direction. symbol "md" is the ball matrix size in the "d" direction. "e" represents the solder ball grid pitch. dimension "b" is measured at the ma ximum ball diameter in a plane solder ball position designation per jep95, section 3, spp-020. "+" indicates the theoretical center of depopulated solder a1 corner to be identified by chamfer, laser or ink mark 8. 7. 6. notes: 5. 4. 3. 2. 1. all dimensions are in millimeters. sd b ee ed me n 0.25 0.25 bsc 0.50 bsc 0.50 bsc 0.30 100 10 0.35 dimensions d1 md e1 e d a a1 symbol 0.16 min. - 4.50 bsc 4.50 bsc 10 6.00 bsc 6.00 bsc nom. - 1.00 - max. se 0.25 bsc d1 e1 100x?b a sd se ee 5 6 6 ?0.15 c m c ?0.05 m ab e d top view bottom view side view a1 corner 7 0.10 2x c ed jedec specification no. ref. : mo-195c. 9. b 0.10 2x c c a1 0.08 c 0.10 c detail a (datum a) (datum b) detail a - a metalized mark, indentation or other means. "sd" = ed/2 and "se" = ee/2. parallel to datum c. "sd" or "se" = 0. size md x me. a1 corner balls. a 1 2 3 4 b c d e f g h 65 j 7 8 9 10 k 51-85209 *f
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 39 of 43 acronyms reference documents usb 2.0 specification usb 3.0 specification battery charging specification document conventions units of measure table 15. acronyms used in this document acronym description aca accessory charging adapter assp application-specific standard product bc battery charging cdp charging downstream port ds downstream dcp dedicated charging port dnu do not use dwg device working group eeprom electrically erasable programmable read-only memory fs full-speed fw firmware gnd ground gpio general-purpose input/output hs hi-speed isp in-system programming i/o input/output ls low-speed nc no connect otg on-the-go pid product id por power-on reset rom read-only memory scl serial clock sda serial data ss superspeed tt transaction translator us upstream vid vendor id table 16. units of measure symbol unit of measure c degree celsius ? ohm gbps gigabit per second kb kilobyte khz kilohertz k ? kiloohm mbps megabit per second mhz megahertz a microampere ma milliampere ms millisecond mw milliwatt ns nanosecond ppm parts per million vvolt
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 40 of 43 silicon revision history this datasheet is appl icable for the usb-if certified (tid# 330 000060) hx3 rev. *d and rev. *c silicon. rev. *d: this silicon revision improves the yield of hx3, and i s drop-in compatible for all the part numbers. there is no need to change the board design or layout to use the hx3 rev. *d silicon. prod ucts are completely compatible with the hx3 rev. *c silicon. rev. *c: this silicon revision fixes the errata applicable to t he rev. *a silicon. the following table defines the ch anges between rev. *a, rev. * c, and rev. *d silicon. method of identification markings on row 3 of t he hx3 package differ entiate rev. *d sili con from rev. *c silicon and rev. *a silicon as indicated in th e example below. cypress maintain s traceability of product to waf er level, including wafer fabri cation location, through the lot number marked on the package. no. items part numbers rev. *a rev. *c rev. *d 1 usb-if compliance all requires firmware on external eeprom no external eeprom required no external eeprom required 2 fs-only hub or host connected to hx3 upstream port all not supported supported supported 3 suspend power all 90 mw 37.8 mw 37.8 mw hx3 rev *a silicon hx3 rev *c silicon hx3 rev *d silicon
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 41 of 43 document history page document title: cyusb330x/cyusb 331x/cyusb332x/cyusb230x, hx3 us b 3.0 hub document number: 001-73643 revision ecn orig. of change submission date description of change *e 4271496 murt 02/21/2014 changed status from preliminary to final . *f 4291210 murt 02/25/2014 po st to external web. *g 4308926 murt 03/14/2014 updated system interfaces : updated configuration options : updated hx3 as i2c slave : updated table 7 . *h 4463533 murt 08/01/2014 updated features : updated tid#. updated electrical specifications : updated power consumption : updated table 9 : updated details corresponding to suspend power. removed errata. *i 4483117 rajm 08/22/2014 added silicon revision history . *j 4499514 rajm 09/15/2014 added 100-ball bga package information i n all instances across the document. updated ordering information : updated table 11 : updated part numbers. updated package diagrams : added spec 51-85209 rev. *d. *k 4582512 prji 11/28/2014 updated hx3 product options : updated table 1 . updated pin information : updated table 4 . *l 4632890 hbm 01/20/2015 updated pin information : updated figure 12 . updated figure 13 . updated table 4 . added packaging . updated package diagrams : spec 51-85209 C changed re vision from *d to *e. *m 4669639 hbm 02/24/2015 no technical updates. completing sunset review. *n 4764583 hbm 05/13/2015 updated package diagrams : spec 001-76569 C changed revision from *a to *b. updated silicon revision history . updated method of ide ntification . *o 4941772 hbm 11/25/2015 updated hx3 product options : updated table 1 : included cyusb2302-68ltxi and cyusb2304-68ltxi part numbers rel ated information. updated ordering information : updated table 11 : updated part numbers.
cyusb330x/cyusb331x cyusb332x/cyusb230x document number: 001-73643 rev. *r page 42 of 43 *p 5466603 hbm 10/20/2016 updated features : replaced usb 3.0-cert ified hub, tid# 330000060 with usb-if c ertified hub, tid# 330000060, 30000074. updated package diagrams : spec 51-85209 C changed re vision from *e to *f. updated to new template. completing sunset review. *q 5725383 gnkk 05/03/2017 updated th e cypress logo and copyright i nformation. *r 6045135 hbm 01/25/2018 updated hx3 product options : updated table 1 : replaced cyusb2302-68ltxi with cyusb2302 in column heading. replaced cyusb2304-68ltxi with cyusb2304 in column heading. updated ordering information : updated table 11 : updated part numbers. updated ordering code definitions . updated to new template. document history page (continued) document title: cyusb330x/cyusb 331x/cyusb332x/cyusb230x, hx3 us b 3.0 hub document number: 001-73643 revision ecn orig. of change submission date description of change
document number: 001-73643 rev. *r revised january 25, 2018 page 43 of 43 ghost charge? and shared link? are trademarks of cypress semico nductor corporation. cyusb330x/cyusb331x cyusb332x/cyusb230x cypress semiconductor corporation, 2011-2018. this document i s the property of cypress semiconductor corporation and its sub sidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in th is document (software), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and tre aties and does not, except as specifically stated in this parag raph, grant any license under its patents, copyrights, trademar ks, or other intellectual property rights. if the software is not accompani ed by a license agreement and you do not otherwise have a writt en agreement with cypress governing the use of the software, th en cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source cod e form, to modify and reproduce the software solely for use with cypress h ardware products, only internally within your organiation, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributo rs), solely for use on cypress hardware product units, and (2) under those claims of cypresss patents that are infringed by t he software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware produc ts. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no war ranty of any kind, express or implied, with regard to this docu ment or any software or accompanying hardware, includi ng, but not limited to, the im plied warranties of merchantability and fitness for a particula r purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informa tion or programming code, is provided only for reference purpos es. it is the responsibility of the user of this document to properly des ign, program, and test the functionality and safety of any appl ication made of this information and any resulting product. cy press products are not designed, intended, or authoried for use as critical c omponents in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support d evices or systems, other medical devices or systems (including resuscitat ion equipment and surgical implants), pollution control or haa rdous substances management, or other uses where the failure of the device or system could cause personal inury, death, or propert y damage (unintended uses). a critical component is any compo nent of a device or system whose failure to perform can be reas onably expected to cause the failure of the device or system, or to af fect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unint ended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims fo r personal inury or death, ari sing from or related to any unint ended uses of cypress products . cypress, the cypress logo, spansion, the spansion logo, and com binations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tr aveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. sales, solutions, an d legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representati ves, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? 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